JPH0450744B2 - - Google Patents

Info

Publication number
JPH0450744B2
JPH0450744B2 JP61057439A JP5743986A JPH0450744B2 JP H0450744 B2 JPH0450744 B2 JP H0450744B2 JP 61057439 A JP61057439 A JP 61057439A JP 5743986 A JP5743986 A JP 5743986A JP H0450744 B2 JPH0450744 B2 JP H0450744B2
Authority
JP
Japan
Prior art keywords
metal substrate
copper plate
oxide film
layer
aluminum oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61057439A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62214632A (ja
Inventor
Akira Kazami
Jusuke Igarashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP61057439A priority Critical patent/JPS62214632A/ja
Publication of JPS62214632A publication Critical patent/JPS62214632A/ja
Publication of JPH0450744B2 publication Critical patent/JPH0450744B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Wire Bonding (AREA)
JP61057439A 1986-03-14 1986-03-14 混成集積回路 Granted JPS62214632A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61057439A JPS62214632A (ja) 1986-03-14 1986-03-14 混成集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61057439A JPS62214632A (ja) 1986-03-14 1986-03-14 混成集積回路

Publications (2)

Publication Number Publication Date
JPS62214632A JPS62214632A (ja) 1987-09-21
JPH0450744B2 true JPH0450744B2 (en]) 1992-08-17

Family

ID=13055686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61057439A Granted JPS62214632A (ja) 1986-03-14 1986-03-14 混成集積回路

Country Status (1)

Country Link
JP (1) JPS62214632A (en])

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5130274A (en) * 1991-04-05 1992-07-14 International Business Machines Corporation Copper alloy metallurgies for VLSI interconnection structures
DE4334127C1 (de) * 1993-10-07 1995-03-23 Mtu Muenchen Gmbh Metallkernleiterplatte zum Einschieben in das Gehäuse eines Elektronikgerätes
KR101204191B1 (ko) * 2010-11-02 2012-11-23 삼성전기주식회사 방열기판
DE102015111667A1 (de) * 2015-07-17 2017-01-19 Rogers Germany Gmbh Substrat für elektrische Schaltkreise und Verfahren zur Herstellung eines derartigen Substrates
CN210157469U (zh) * 2018-12-29 2020-03-17 广东生益科技股份有限公司 金属基覆铜箔层压板

Also Published As

Publication number Publication date
JPS62214632A (ja) 1987-09-21

Similar Documents

Publication Publication Date Title
US6328201B1 (en) Multilayer wiring substrate and method for producing the same
JPH0218573B2 (en])
JPH0450744B2 (en])
JP2833642B2 (ja) 多層配線基板及びその製造方法
US3787961A (en) Chip-shaped, non-polarized solid state electrolytic capacitor and method of making same
JPH06151913A (ja) 電極形成法
JP2542794B2 (ja) 配線板の製造方法
JPH0450743B2 (en])
JP3420469B2 (ja) 配線基板
JP3499061B2 (ja) 多層窒化アルミニウム回路基板
JPS6227675B2 (en])
JP2000058995A (ja) セラミック回路基板及び半導体モジュール
JP3562074B2 (ja) 半導体パッケージ用樹脂フレーム及び半導体パッケージの製造方法
JP2817873B2 (ja) 混成集積回路基板及びその製造方法
JP2000340594A (ja) 転写バンプシートとその製造方法
JPH0636601Y2 (ja) 回路基板
JP3950950B2 (ja) セラミック配線基板の製造方法
JPH02164094A (ja) 印刷配線板の製造方法
JPS626710Y2 (en])
SU367979A1 (ru) Способ контактно-реактивной пайки изделий
JPH10209593A (ja) 2層配線基板、及びその製造方法
JPH06310628A (ja) 混成集積回路
JPS58102596A (ja) 金属芯印刷配線板
JPH08335777A (ja) 多層薄膜配線基板
JPH0763109B2 (ja) セラミック回路基板の製造方法